Scheduling algorithms for Real-Time embedded processing

Good Introduction to Rate Monotonic scheduling algorithm.
http://www.netrino.com/Embedded-Systems/How-To/RMA-Rate-Monotonic-Algorithm

Know about other scheduling algorithms.

A good insight.
http://www.csie.ntu.edu.tw/~ktw/rts/ch-short-course-uni.pdf

Theory about other scheduling algorithms.
http://www.dauniv.ac.in/downloads/EmbsysRevEd_PPTs/Chap_8Lesson22EmsysNewOtherScdmethods.pdf

Perl for the day: while loop construct

use strict;
use warnings;

# to play cricket in my perl program

print "\nPress any of 0 to 9\n\n";

use Term::ReadKey;
my $bat = 1;
my $player;
my $num;
my $team;
my $ran = 0;
my $spot = 0;
my @res;

ReadMode 'cbreak';

while (++$spot < 3) {
    print "Team: ", $spot, "\n";
    $num = 0;
    $team = 0;
    while (++$num < 11) {
        print "    Player ", $num, ": ";
        $player = 0;
        while ($bat != 0) {
            $bat = int(ReadKey(0));
            $ran = int(rand(12345)) + $bat;
            $bat = $ran % 6;
            if ($bat != 0) {
                print $bat, "+";
            }
            $player += $bat;
        }
        print "=", $player, "\n";
        $team += $player;
        $bat = 1;
    }
    print "  Total score = ", $team,"\n";
    $res[$spot] = $team;
}
if ($res[1] > $res[2]) {
    print "Team 1 Won\n";
} elsif ($res[2] > $res[1]) {
    print "Team 2 Won\n";
} else {
    print "Match Tie\n";
}

Perl for the day: for loop construct handling array

use strict;
use warnings;

# fibonacci sequence/series using array in Perl

my $i;
my @ser = (0, 1);

for ($i = 2; $i < $ARGV[0]; $i++) {
    $ser[$i] = $ser[$i - 1] + $ser[$i - 2];
}

for ($i = 0; $i < $ARGV[0]; $i++) {
    print $ser[$i]," ";
}

dcbst - Data Cache Block Store instruction in PowerPC

If the byte specified by the effective address (EA) is cached by the data cache and the cache-line is modified (dirty), the entire contents of the cache-line are written to system memory. After the store completes, the cache-line is marked as unmodified (not dirty). But, the cache-line is not invalidated

dcba, dcbz, dcbt, dcbtst cache control instructions in PowerPC

dcba - Data Cache Block Allocate

dcbz - Data Cache Block set to Zero

dcbt - Data Cache Block Touch

dcbtst - Data Cache Block Touch for Store

are called data-cache hint instructions. These instructions are used to improve the memory performance by avoiding cache miss. With these instructions, the cache lines corresponding to memory locations that are likely to be accessed in the near future can be allocated speculatively to avoid cache-miss. For example, with dcbt and dcbtst instructions, if the byte specified by the effective address (EA) is cacheable and is not currently cached by the data cache, the cacheline containing that byte is loaded into the data cache from main memory.

dcbt and dcbtst instructions are further optimized to dcba and dcbz instructions where the cache lines are allocated for the effective address (EA) without copying data from system memory where the contents of the main memory are no longer needed or the memory block can be initialized to zero.

What is Big Endian and Little Endian?: In Words

Big Endian means Most Significant Byte (MSB) is at the lowest address.

Little Endian means Most Significant Byte (MSB) is at the highest address.

Advantages of FPGA

The main advantage of FPGA is that high speed and parallel processing can be easily implemented.Industrial embedded systems typically require high I/O counts, making parallel IP blocks in FPGA fabric well-suited for managing analog, digital, and communications interrupts that would otherwise bog down an embedded processor. For example, in Telecom, Video processing, Digital Signal processing, High speed Real-Time processing, fixed processing logic can be implemented in Hardware through FPGA.

Then, other advantages such as:
www.men.de/docs-ext/expertise/pdf/fpga_advantages.pdf
www.canterbury-consulting.co.uk/.../fpga.../56-advantages-of-fpga-devices

The PowerPC Architecture: Software Programming summary

Things to be take care when programming or porting to PowerPC CPU architecture.

The PowerPC Architecture: A programmer's view
class.ee.iastate.edu/cpre211/handouts/xc_ibm_pwrpc42.pdf

In Japanese:
http://japan.xilinx.com/xcell/xl42/xcell_42_05.pdf

RTC Magazine`s April Issue

Get April issue of RTC magazine in the following link:

http://upload.rtcgroup.com/rtcmagazine/digital/pdf/rtc1104.pdf

Perl for the day: for loop construct

use strict;
use warnings;

# fibonacci sequence/series in Perl

my $cur = 1;
my $prev = 0;
my $i, my $tmp;

print $prev, " ";

for ($i = 0; $i < $ARGV[0]; $i++) {
    print $cur, " ";
    $tmp = $cur;
    $cur += $prev;
    $prev = $tmp;
}